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ht48ra0-5 remote type 8-bit otp mcu rev.1.50 1 august 13, 2012 features operating voltage: f sys =4mhz at v dd =2.0v~3.6v (lvr enabled) f sys =4mhz at v dd =1.8v~3.6v (lvr disabled) oscillator types: external high frequency crystal -- hxt internal high frequency rc -- hirc 1k 14 program memory 32 8 data ram one-level subroutine nesting 17 bidirectional i/o lines fully integrated internal 4095khz oscillator requires no external components one programmable carrier output - using 9-bit timer carrier output pin (rem) build-in ir driver (350ma@3.0v) watchdog timer low voltage reset function power-down and wake-up features reduce power consumption 14-bit table read instructions up to 1 s instruction cycle with 4mhz system clock 62 powerful instructions all instructions executed in 1 or 2 machine cycles bit manipulation instructions ht48ra0-5 use in external ir driver ht48ra0-5b use in internal ir driver 16-pin nsop and 20-pin ssop packages general description the ht48ra0-5 is 8-bit high performance, risc archi - tecture microcontroller device specifically designed for multiple i/o control product applications. the advantages of low power consumption, i/o flexibil- ity, timer functions, watchdog timer, halt and wake-up functions, as well as low cost, enhance the versatility of this device to suit a wide range of application possibili - ties such as industrial control, consumer products, and particularly suitable for use in products such as infrared remote controllers and various subsystem controllers.
block diagram pin assignment pin description pin name i/o configuration option description pa0~pa7 i/o bidirectional 8-bit input/output port with pull-high resistors. software in- structions determine if the pin is an nmos output or schmitt trigger input. each pin can have a wake-up function if configured as an input pin. pb0~pb4 pb5/osc2 pb6/osc1 pb7 i/o osc bidirectional 8-bit input/output port with pull-high resistors. software in - structions determine if the pin is an nmos output or schmitt trigger input. each pin can have a wake-up function if configured as an input pin. pb5 and pb6 are pin-shared with the external crystal pins named osc2 and osc1 respectively determined by a configuration option. pc0/res i/o res bidirectional 1-bit input/output port without a pull-high resistor. software in - structions determine if the pin is an nmos output or schmitt trigger input. this pin has the capability of wake-up when it is configured as an input pin. pc0 is pin-shared with the external reset pin named res determined by a configuration option. rem o remdrv carrier output dual function pin. rem is a cmos carrier output pin with an initial low level after a reset. rem pin is a high sink current nmos open drain carrier output pin which will be in a floating condition after a reset. the selection of rem or remdrv is determined by a configuration option. vdd positive power supply vss negative power supply, ground ht48ra0-5 rev.1.50 2 august 13, 2012

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absolute maximum ratings supply voltage ...........................v ss 0.3v to v ss +4.0v storage temperature ............................ 50 cto125 c input voltage..............................v ss 0.3v to v dd +0.3v operating temperature........................... 20 cto70 c i ol total ..............................................................150ma i oh total............................................................ 100ma total power dissipation .....................................500mw note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage lvr disable 1.8 3.6 v lvr enable 2.0 3.6 v i dd operating current 3v no load, f sys =4mhz 0.5 1.2 ma i stb1 standby current 3v no load, system halt, wdt disable 0.1 1.0 a i stb2 standby current 3v no load, system halt, wdt enable 5.0 a v il input low voltage for i/o ports 0 0.2v dd v v ih input high voltage for i/o ports 0.8v dd v dd v v il input low voltage for res ports 0 0.4v dd v v ih input high voltage for res ports 0.9v dd v dd v i oh rem output source current 3v v oh =0.9v dd 5 7 ma i ol1 pa, pb, rem output sink current 3v v ol =0.1v dd 612 ma i ol2 pc0 sink current 3v v ol =0.1v dd 0.8 1.2 ma i ol3 rem output sink current 3v v ol =0.2v dd 300 350 ma r ph pull-high resistance of port a, port b 3v 100 150 200 k v lvr low voltage reset voltage 1.8 1.9 2.0 v v por v dd start voltage to ensure power-on reset 100 mv r por v dd rise rate to ensure power-on reset 0.035 v/ms ht48ra0-5 rev.1.50 3 august 13, 2012
a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock 1.8v~ 3.6v ta= -20 c~70 c 400 4000 khz f hirc system clock (hirc) 2.2v~ 3.6v ta= -20 c~50 c 4013 4095 4179 khz t sst system start-up timer period power-up or wake-up from halt 1024 t sys t wdtosc watchdog oscillator 3v 45 90 180 s t lvr low voltage width to reset 0.25 1.00 2.00 ms t por power-on reset low pulse width 1 s note: t sys =1/f sys to maintain the accuracy of the internal hirc oscillator frequency, a 0.1 f decoupling capacitor should be connected between vdd and vss and located as close to the device as possible. power-on reset characteristics symbol parameter test conditions min. typ. max. unit v dd conditions v por vdd start voltage to ensure power-on reset 100 mv rr vdd vdd raising rate to ensure power-on reset 0.035 v/ms t por minimum time for vdd stays at v por to ensure power-on reset 1 ms ht48ra0-5 rev.1.50 4 august 13, 2012 ' "
characteristics curves ht48ra0-5 rev.1.50 5 august 13, 2012
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ht48ra0-5 rev.1.50 6 august 13, 2012 functional description execution flow the main system clock is derived from either an external crystal oscillator which requires the connection of the external crystal or resonator or an internal rc oscillator which requires no external component for its operation. it is internally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cy - cles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute within one cycle. if an instruc - tion changes the program counter, two cycles are required to complete the instruction. program counter pc the 10-bit program counter (pc) controls the sequence in which the instructions stored in program memory are executed and its contents specify a maximum of 1024 addresses. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 locations. when a control transfer takes place, an additional dummy cycle is required.

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9 # ( " ! ) , 0 ( . ' 0 ! # ) " execution flow mode program counter *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0000000000 skip program counter + 2 loading pcl *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program counter note: *9~*0: program counter bits s9~s0: stack register bits #9~#0: instruction code bits @7~@0: pcl bits
ht48ra0-5 rev.1.50 7 august 13, 2012 program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data and table and is organized into 1024 14 bits, ad - dressed by the program counter and table pointer. certain locations in the program memory are reserved for special usage: location 000h this area is reserved for the initialization program. af - ter a device reset, the program always begins execu - tion at location 000h. table location any location in the program memory space can be used as a look-up table. the instructions tabrdc [m] (the current page, one page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory register, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the ta - ble is well-defined, the other bits of the table word are transferred to the lower portion of tblh, the remain - ing 2 bits are read as 0 . the table higher-order byte register (tblh) is read only. the table pointer (tblp) is a read/write register (07h), where p indicates the table location. before accessing the table, the location must be placed in tblp. the tblh is read only and cannot be restored. all table related instructions need 2 cycles to complete the operation. these areas may function as normal program memory depending upon the requirements. stack register stack this is a special part of the memory used to save the contents of the program counter only. the stack is orga- nized into one level and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer and is neither readable nor writeable. at a sub - routine call the contents of the program counter are pushed onto the stack. at the end of a subroutine sig - naled by a return instruction, ret, the program counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a call is subsequently exe - cuted, stack overflow occurs and the first entry will be lost and only the most recent return address is stored. data memory ram the data memory is divided into two functional groups: special function registers and general purpose data memory (32 8). most are read/write, but some are read only. the remaining space before the 20h is reserved for fu - ture expanded usage and reading these locations will return the result 00h. the general purpose data mem - ory, addressed from 20h to 3fh, is used for data and control information under instruction command. all data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. except for some dedicated bits, each bit in the data memory can be set and reset by the set [m].i and clr [m].i instructions, respec- tively. they are also indirectly accessible through memory pointer register (mp;01h). indirect addressing register location 00h is an indirect addressing register that is not physically implemented. any read/write operation to [00h] accesses the data memory pointed to by mp (01h). reading location 00h itself indirectly will return the result 00h. writing indirectly results in no operation. the memory pointer register mp (01h) is a 7-bit register. bit 7 of mp is undefined and reading will return the result 1 . any writing operation to mp will only transfer the lower 7-bits of data to mp. 6 " > ' " ! ' 0 ' ' ) ' 7 ' 0 ! 4
! + ' ( 2 * . 4 ! + ) " ! < ! 3 & ( = 0 6 2 * . 4 ! + ) " ! < ! 3 & ( = : : 6 0 : : 6 program memory instruction(s) table location *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: *9~*0: table location bits @7~@0: table pointer bits p9~p8: current program counter bits
ht48ra0-5 rev.1.50 8 august 13, 2012 accumulator the accumulator closely relates to alu operations. it is also mapped to location 05h of the data memory and is capable of carrying out immediate data operations. data movement between two data memory locations has to pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operation. the alu provides the following functions. arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the contents of the status register. status register status this 8-bit status register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf) and watchdog time-out flag (to). it also records the status information and con - trols the operation sequence. with the exception of the to and pdf flags, the other status register bits can be altered by instructions like most other register. any data written into the status regis- ter will not change the to or pdf flags. in addition it should be noted that operations related to the status reg- ister may give different results from those intended. the to and pdf flags can only be changed by the watchdog timer overflow, device power-up, clearing the watchdog timer and executing the halt instruction. the z, ov, ac and c flags generally reflect the status of the latest operations. 4 " ' ) ! . 4 ( " ! " # , 2 2 2 6 -
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: 6 : 6 ram mapping bit no. label function 0c c is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a ro - tate through carry instruction. 1ac ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. 3ov ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared when either a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6~7 unused bit, read as 0 status (0ah) register
ht48ra0-5 rev.1.50 9 august 13, 2012 in addition, on executing a subroutine call, the status register will not be automatically pushed onto the stack. if the contents of the status are important and if the sub - routine can corrupt the status register, precautions must be taken to save it properly. oscillator configuration in this device there are two methods of generating the system clock, one external crystal oscillator and one in - ternal rc oscillator. external crystal/resonator oscillator hxt the external crystal/ceramic system oscillator is one of the system oscillator choices, which is selected via a configuration option. for the crystal oscillator configuration, the connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation. two external capacitors may be required to be connected as shown. however, the feedback resistor named rf shown in the following diagram for the crystal oscillator to oscillate properly can be selected as either an internally or externally connected type via a configuration option. when the external connection type of the feedback resistor is selected, the recommended value of the external con - nected feedback resistor ranges from 300k to 500k . using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be con- nected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer
s specification. crystal oscillator c1 and c2 values crystal frequency c1 c2 4mhz 8pf 10pf note: c1 and c2 values are for guidance only. crystal recommended capacitor values internal rc oscillator hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the inter - nal rc oscillator has a fixed frequency of 4095khz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process varia - tions on the oscillation frequency are minimised. as a result, at a power supply ranging from 2.2v to 3.6v and in a temperature range from -20 cto50 cde - grees, the fixed oscillation frequency of 4095khz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no ex - ternal pins for its operation, i/o pins pb5 and pb6 are free for use as normal i/o pins.
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ht48ra0-5 rev.1.50 10 august 13, 2012 watchdog timer wdt the wdt clock source is implemented by the instruction clock which is the system clock divided by 4 or the inter - nal rc oscillator with the frequency of 12khz. the clock source is processed by a frequency divider and a prescaler to provide various time out periods. wdt time out period = clock source 2 n where n= 8~11 selected by a configuration option. the wdt timer is designed to prevent a software mal - function or sequence jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by configuration option. if the watchdog timer is disabled, all the executions related to the wdt result in no operation and the wdt will lose its protection pur - pose. in this situation the logic can only be restarted by external logic. a wdt overflow under normal operation will initialise a chip reset and set the status bit to . to clear the con - tents of the wdt prescaler, two methods are adopted, software instructions or a halt instruction. there are two types of software instructions. one type is the single in - struction clr wdt , the other type comprises two in - structions, clr wdt1 and clr wdt2 . of these two types of instructions, only one can be active depending on the configuration option clr wdt times selection op- tion .ifthe clr wdt is selected (i.e.. clr wdt times equal one), any execution of the clr wdt instruction will clear the wdt. in case clr wdt1 and clr wdt2 are chosen (i.e.. clr wdt times equal two), these two in- structions must be executed to clear the wdt; otherwise, the wdt may reset the chip due to a time-out. power down operation halt the power-down mode is initialised by the halt in - struction and results in the following: the system oscillator turns off and the wdt stops. the contents of the on-chip data memory and regis - ters remain unchanged. wdt prescaler is cleared. all i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can quit the halt mode by means of an ex - ternal falling edge signal on port b. by examining the to and pdf flags, the reason for chip reset can be deter - mined. the pdf flag is cleared when the system powers up or when a clr wdt instruction is executed and is set when the halt instruction is executed. the to flag is set if the wdt time-out occurs during normal operation. the port b wake-up can be considered as a continuation of normal execution. each bit in port b can be independ - ently selected to wake up the device by the code option. awakening from an i/o port stimulus, the program will resume execution of the next instruction. once a wake-up event(s) occurs, it takes 1024 t sys (system clock periods) to resume normal operation. in other words, a dummy cycle period will be inserted after the wake-up. to minimize power consumption, all i/o pins should be carefully managed before entering the halt status. 0 @ d * + ' ! . 0 " " ( ) ) " < * + ' = $ ! ' " * . e " ) " ) " ! $ : " c . " 0 # ! ' > ' & " @ < 0 f g

= - 1 $ ! <
h ! = 0 @ ' . ' 0 4 ' 0 0 @ ' . ' 0 4 ' 0 @ watchdog timer
ht48ra0-5 rev.1.50 11 august 13, 2012 reset there are several ways in which a reset can occur: power on reset res pin reset low voltage reset wdt time-out reset during normal operation some registers remain unchanged during reset condi - tions. most registers are reset to the initial condition when the reset conditions are met. by examining the pdf and to flags, the program can distinguish between different chip resets. to pdf reset conditions 0 0 power-on reset uu res or lvr reset during normal operation 1u wdt time-out reset during normal operation 11 wdt time-out reset during power-down mode note: u means unchanged. to guarantee that the system oscillator has started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys - tem powers up or when the system awakes from a halt state. when a system power up occurs, an sst delay is added during the reset period. any wake-up from halt will en - able the sst delay. the functional unit chip reset status is shown below. program counter 000h wdt prescaler clear input/output ports input mode stack pointer points to the top of the stack carrier output low level state or floating state* * determined by configuration option $ ) & ! " ( " 6 2 3 " * 0 ! " " ' 0
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2 reset configuration 3 " * 0 ! " ( " ! ' " * . , 0 " 0 ) ! ! " ( " reset timing chart 5
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i i note: * it is recommended that this component is added for added esd protection ** it is recommended that this component is added in environments where power line noise is significant. external res circuit
ht48ra0-5 rev.1.50 12 august 13, 2012 input/output ports there are up to 17 bidirectional input/output lines in the device, labeled pa, pb and pc which are mapped to [12h], [14h] and [16h] of the data memory, respec - tively. each line of pa and pb can be selected as nmos output or schmitt trigger input with pull-high resistor by a software instruction. pc0 can be used as an input line with schmitt trigger but without pull-high resistor or as the external res pin determined by the configuration option. when the i/o ports are used for input operation, these ports are non-latched, that is, the inputs should be ready at the t2 rising edge of the instruction mov a, [m] (m=12h, 14h or 16h). for i/o ports output operations, all data is latched and remains unchanged until the out - put latch is rewritten. when the i/o ports are used for input operations, it should be noted that before reading data from the pads, a 1 should be written to the related bits to disable the nmos device. that is, the instruction set [m].i (i=0~7 for pa and pb, i=0 for pc) is executed first to disable re - lated nmos device, and then mov a, [m] to get stable data. after chip reset, the i/o ports remain at a high level input line. each bit of the i/o ports output latches can be set or cleared by the set [m].i and clr [m].i (m=12h, 14h or 16h) instructions respectively. some instructions first input data and then follow the output operations. for example, set [m].i, clr [m], cpl [m] and cpla [m] read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. each line of the i/o ports has a wake-up capability when the relevant pin is configured as an input line. the chip reset status of the registers is summarised in the following table: register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (halt)* program counter 000h 000h 000h 000h mp -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pc ---- ---1 ---- ---1 ---- ---1 ---- ---u tsr0 0000 0000 0000 0000 0000 0000 uuuu uuuu tsr1 1000 0000 1000 0000 1000 0000 uuuu uuuu carl0 0000 0000 0000 0000 0000 0000 uuuu uuuu carl1 0000 0000 0000 0000 0000 0000 uuuu uuuu carh0 0000 0000 0000 0000 0000 0000 uuuu uuuu carh1 0000 0010 0000 0010 0000 0010 uuuu uuuu note: u means unchanged x means unknown - stands for unimplemented
ht48ra0-5 rev.1.50 13 august 13, 2012 j h j ! + . ( $ ' " % ' 4 ! " ( " " & ! ! " ' ( " # ( " ! $ " * . 4 ! < = pc0 input/output port 0 @ ' . ' 0 ! 4 ' 0 ! . 4 . rem output pin structure timer the timer is an internal unit for creating a remote control transmission pattern. as shown, it consists of a 9-bit down counter (t8 to t0), a flag (t9) permitting the 1-bit timer output, and a zero detector. no. label function 0~7 t0~t7 down counter tsr0 (18h) register no. label function 0 t8 down counter 1t9 timer enable, initial value is 0. 2~6 unused bit, read as 0. 7 toef timer operation end flag, initial value is 1. tsr1 (19h) register timer operation the timer starts counting down when a value other than 0 is set for the down counter with a timer manipulation instruction. the timer manipulation instructions for mak - ing the timer start operation are shown below: mov a,xxh ; xx = 00h ~ ffh mov tsr0,a mov a,xxh ; xx 01h, t8 mov tsr1,a set tsr1.1 ; the timer is started by set t9=1 addition notes for the 9-bit timer: writing to tsr0 will only put the written data to the tsr0 register (t7~t0) and writing to tsr1 (t8) will transfer the specified data and contents of tsr0 to the down counter. toef will be cleared after the data transferred from tsr1 and tsr0 to the down coun - ter is completed and then wait until tsr1.1 is set by user. setting tsr1.1=1, the timer will start counting. the timer will stop when its count is equal to 0 and then toef is set equal to 1. j h j ! + . ( $ ' " % ' 4 ! " ( " " & ! ! " ' ( " $ " . ) ) * . 4 g g
# ( " ! $ " * . 4 ! < e ! = pa and pb input/output ports
ht48ra0-5 rev.1.50 14 august 13, 2012 if the tsr1.1 is cleared during the timer counting, the timer will be stopped. once the tsr1.1 is set (10 1), the down counter will reload data from t8~t0, and then the down counter begins counting down with the new load data. if tsr1.1 and toef are equal to 1 both, the timer can re-start, after new data is written to tsr0, tsr1 (t0~t8) in sequence. note: if the contents of the down counter is 000h, set the t9 to start the timer counting, the timer will only count 1 step. the timer output time=64/f sys . [ (0+1) 64/f sys =64/f sys ] the down counter is decremented ( 1) in the cycle of 64/f sys . if the value of the down counter becomes 0, the zero detector generates the timer operation end sig - nal to stop the timer operation. at this time, toef will be set to 1 . the output of the timer operation end signal is continued while the down counter is 0 and the timer is stopped. the following relational expression applies be - tween the timer
s output time and the down counter
s set value. timer output time = (set value+1) 64/f sys an example is shown below. mov a,0ffh mov tsr0,a mov a,01h mov tsr1,a set tsr1.1 in the case above, the timer output time is as follows. (set value+1) 64/f sys = (511+1) 16s = 8.192ms setting the t9 bit channels the timer to the rem pin. the rem pin will be a combination of the timer and carrier sig - nals. note: the carrier output results if bit 9 of the high-level period setting modulo register (carh) is cleared ( 0).
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= ! / ! @ d ' " ! . 4 . timer output when carrier is not output
ht48ra0-5 rev.1.50 15 august 13, 2012 carrier output carrier output generator the carrier generator consists of a 9-bit counter and two modulo registers for setting the high-level and low-level peri - ods - carh and carl respectively. register bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 carl0 cl.7 cl. cl. cl. cl.3 cl.2 cl.1 cl.0 carl1 fix 0 cl.8 carh0 ch.7 ch.6 ch.5 ch.4 ch.3 ch.2 ch.1 ch.0 carh1 ch.9 (cary) ch.8 carl0 (1ah) register, carl1 (1bh), carh0 (1ch) register, carh1 (1dh), register note: 1. carh1.1 (cary) initial value is 1. 2. carl1.2 (carh1.2)~carl1.7 (carh1.7) are unused bits, read as 0. the carrier duty ratio and carrier frequency can be determined by setting the high-level and low-level widths using the respective modulo registers. each of these widths can be set in a range of 500ns to 64 satf sys = 4mhz. carh (carh1.0, carh0.7~carh0.0) and carl (carl1.0, carl0.7~carl0.0) are read and written using in - structions. example: mov a,xxh ; xxh = 00h~ffh mov carl0,a mov a,xxh ; xxh 01h, cl.8 (carl1.0) mov carl1,a mov a,xxh ; xxh = 00h~ffh mov carh0,a mov a,xxh ; xxh 02h, ch.8 (carh1.0) mov carh1,a clr carh1.1 ; the carrier is started by clearing cary(carh1.1)= 0 " ) " 4 @ d ! < ; " ! = 2
2 * + ' ! . 0 " @ d 2 5 < = ; " !
5 2 5 2 5 2 5 2 5 2 5 2 5 2 5 2 5
2 5 & . ) ! " ' ( " ! @ ! ( " ' 0 ! % " ! ) 3 * ) " > " ) ! 4 " ' & < 2 5 g 2 5 = 2 6
6 6 5 d 6 5 6 5 6 5 6 5 6 5 6 5 6 5 6 5
6 5 & . ) ! " ' ( " ! @ ! ( " ' 0 ! % " ! % ' % * ) " > " ) ! 4 " ' & < 6 5 g 6 5 = 6 : : ' " ' 0 ) % ) " configuration of remote controller carrier generator note: 1. bit 9 of the modulo register for setting the low-level period (carl) is fixed to 0. 2. t9: flag that enables timer output (timer block, see timer configuration)
ht48ra0-5 rev.1.50 16 august 13, 2012 the values of carh and carl can be calculated from the following expressions. carl (carl1.0, carl0.7~carl0.0) = ( f sys (1d) t) 1 carh (carh1.0, carh0.7~carh0.0) = ( f sys d t) 1 d: carrier duty ratio ( 0 ) . " 9
= ! / ! @ d timer output when carrier is output note: when the carrier signal is active and during the time when the signal is high, if the timer output should go low, the carrier signal will first complete its high level period before going low.
ht48ra0-5 rev.1.50 17 august 13, 2012 carh1.1 timer output enable flag (t9: tsr1.1) 9-bit down counter rem function (cmos output) remdrv function (nmos output) 00 0 low-level output floating output 0 0 other than 0 01 0 64/f sys (with carrier output) 64/f sys (with carrier output) 0 1 other than 0 carrier output (note) carrier output 10 low-level output floating output 11 high-level output low-level output rem pin output control note: input values in the range of 001h to 1ffh to carh (carh1.0, carh0.7~carh0.0) and carl (carl1.0, carl0.7~carl0.0). caution: carh (carh1.0, carh0.7~carh0.0) and carl (carl1.0, carl0.7~carl0.0) must be set while the rem pin is at a low level (t 9=0ort0tot8=0). carh (carh1.0, carh0.7~carh0.0) carl (carl1.0, carl0.7~carl0.0) t h ( s) t l (s) t( s) f c (khz) duty 20h 20h 8.25 8.25 16.50 60.60 1/2 22h 45h 8.75 17.50 26.25 38.10 1/3 22h 46h 8.80 17.60 26.40 37.90 1/3 24h 49h 9.26 18.52 27.78 36.00 1/3 carrier frequency setting (f sys =4mhz) carh (carh1.0, carh0.7~carh0.0) carl (carl1.0, carl0.7~carl0.0) t h ( s) t l (s) t( s) f c (khz) duty 25h 4bh 9.256 18.510 27.770 36 1/3 23h 47h 8.770 17.540 26.310 38 1/3 18h 30h 5.950 11.900 17.850 56 1/3 carrier frequency setting (f sys =4095khz) 2 ' " ! ' 0 ) 6
ht48ra0-5 rev.1.50 18 august 13, 2012 5 2 5 " ( " ! ' 0 ) " ( " i
i ; ) ! 4 " ' 0 " ( " 2 ! " " ! ) " low voltage reset note: *1 to make sure that the system oscillator has stabilised, the sst provides an extra delay of 1024 system clock pulses before entering normal operation. *2 since low voltage has to be maintained in its original state and exceed 1ms, a 1ms delay enters the reset mode. 5
5 5 2 low voltage reset lvr the microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr , such as when changing a battery, the lvr will automatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in this state for a time in excess of 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and will not perform a reset function. the relationship between v dd and v lvr is shown below.
configuration options the following table shows the range of configuration options for the device. all the configuration options must be de - fined to ensure proper system functioning. no. code option oscillator options 1 system oscillator selection - f sys : xtal oscillator without internal feedback resistor xtal oscillator with internal feedback resistor internal 4095khz rc oscillator rem pin options 2 rem or remdrv output function selection watchdog options 3 wdt clock selection - f s : internal rc oscillator or f sys /4 4 wdt function: enable or disable 5 clrwdt instruction selections: 1 or 2 instructions 6 wdt time-out period selections: 2 8 /f s ,2 9 /f s ,2 10 /f s ,2 11 /f s lvr options 7 lvr function: enable or disable reset pin options 8 i/o or res pin selection ht48ra0-5 rev.1.50 19 august 13, 2012
application circuits note: the 0.1uf capacitor is required to ensure that the system clock frequency meets with the specified tolerance in the a.c. characteristics. ht48ra0-5 rev.1.50 20 august 13, 2012

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ht48ra0-5 rev.1.50 21 august 13, 2012 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht48ra0-5 rev.1.50 22 august 13, 2012 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
ht48ra0-5 rev.1.50 23 august 13, 2012 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht48ra0-5 rev.1.50 24 august 13, 2012
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht48ra0-5 rev.1.50 25 august 13, 2012
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1
s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1
s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht48ra0-5 rev.1.50 26 august 13, 2012
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht48ra0-5 rev.1.50 27 august 13, 2012
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht48ra0-5 rev.1.50 28 august 13, 2012
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht48ra0-5 rev.1.50 29 august 13, 2012
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht48ra0-5 rev.1.50 30 august 13, 2012
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht48ra0-5 rev.1.50 31 august 13, 2012
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht48ra0-5 rev.1.50 32 august 13, 2012
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht48ra0-5 rev.1.50 33 august 13, 2012
package information note that the package information provided here is for consultation purposes only. as this information may be updated at regu - lar intervals users are reminded to consult the holtek website ( http://www.holtek.com.tw/english/literature/package.pdf ) for the latest version of the package information. 16-pin nsop (150mil) outline dimensions ms-012 symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.157 c 0.012 0.020 c
0.386 0.394 d 0.069 e 0.050 f 0.004 0.010 g 0.016 0.050 h 0.007 0.010 08 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 3.99 c 0.30 0.51 c
9.80 10.01 d 1.75 e 1.27 f 0.10 0.25 g 0.41 1.27 h 0.18 0.25 08 ht48ra0-5 rev.1.50 34 august 13, 2012

: a 6 l
20-pin ssop (150mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.228 0.244 b 0.150 0.158 c 0.008 0.012 c
0.335 0.347 d 0.049 0.065 e 0.025 f 0.004 0.010 g 0.015 0.050 h 0.007 0.010 08 symbol dimensions in mm min. nom. max. a 5.79 6.20 b 3.81 4.01 c 0.20 0.30 c
8.51 8.81 d 1.24 1.65 e 0.64 f 0.10 0.25 g 0.38 1.27 h 0.18 0.25 08 ht48ra0-5 rev.1.50 35 august 13, 2012

: l a 6
product tape and reel specifications reel dimensions sop 16n (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 ssop 20s (150mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 16.8 +0.3/-0.2 t2 reel thickness 22.20.2 ht48ra0-5 rev.1.50 36 august 13, 2012

carrier tape dimensions sop 16n (150mil) symbol description dimensions in mm w carrier tape width 16.00.3 p cavity pitch 8.00.1 e perforation position 1.750.1 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.55 +0.10/-0.00 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 10.30.1 k0 cavity depth 2.10.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 ssop 20s (150mil) symbol description dimensions in mm w carrier tape width 16.0 +0.3/-0.1 p cavity pitch 8.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 7.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 6.50.1 b0 cavity width 9.00.1 k0 cavity depth 2.30.1 t carrier tape thickness 0.300.05 c cover tape width 13.30.1 ht48ra0-5 rev.1.50 37 august 13, 2012
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ht48ra0-5 rev.1.50 38 august 13, 2012 holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538 tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright 2012 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek
s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw.

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